/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
 * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
 * Author: Chuan Liu <chuan.liu@amlogic.com>
 */

#ifndef __AMLOGIC_C3_SCMI_CLKC_H
#define __AMLOGIC_C3_SCMI_CLKC_H

#define CLKID_DDR_PLL_OSC			0
#define CLKID_DDR_PHY				1
#define CLKID_TOP_PLL_OSC			2
#define CLKID_USB_PLL_OSC			3
#define CLKID_MIPIISP_VOUT			4
#define CLKID_MCLK_PLL_OSC			5
#define CLKID_USB_CTRL				6
#define CLKID_ETH_PLL_OSC			7
#define CLKID_OSC				8
#define CLKID_SYS_CLK				9
#define CLKID_AXI_CLK				10
#define CLKID_CPU_CLK				11
#define CLKID_FIXED_PLL_OSC			12
#define CLKID_GP1_PLL_OSC			13
#define CLKID_SYS_PLL_DIV16			14
#define CLKID_CPU_CLK_DIV16			15

#endif /* __AMLOGIC_C3_SCMI_CLKC_H */
