| Internet-Draft | PLE | August 2022 |
| Gringeri, et al. | Expires 20 February 2023 | [Page] |
This document describes a method for encapsulating high-speed bit-streams as virtual private wire services (VPWS) over packet switched networks (PSN) providing complete signal transport transparency.¶
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This document describes a method for encapsulating high-speed bit-streams as VPWS over packet switched networks (PSN). This emulation suits applications where signal transparency is required and data or framing structure interpretation of the PE would be counter productive.¶
One example is two ethernet connected CEs and the need for synchronous ethernet operation between them without the intermediate PEs interfering or addressing concerns about ethernet control protocol transparency for carrier ethernet services, beyond the behavior definitions of MEF specifications.¶
Another example would be a Storage Area Networking (SAN) extension between two data centers. Operating at a bit-stream level allows for a connection between Fibre Channel switches without interfering with any of the Fibre Channel protocol mechanisms.¶
Also SONET/SDH add/drop multiplexers or cross-connects can be interconnected without interfering with the multiplexing structures and networks mechanisms. This is a key distinction to CEP defined in [RFC4842] where demultiplexing and multiplexing is desired in order to operate per SONET Synchronous Payload Envelope (SPE) and Virtual Tributary (VT) or SDH Virtual Container (VC). Said in another way, PLE does provide an independent layer network underneath the SONET/SDH layer network, whereas CEP does operate at the same level and peer with the SONET/SDH layer network.¶
The mechanisms described in this document follow principals similar to [RFC4553] but expanding the applicability beyond the narrow set of PDH interfaces (T1, E1, T3 and E3) and allow the transport of signals from many different technologies such as Ethernet, Fibre Channel, SONET/SDH [GR253]/[G.707] and OTN [G.709] at gigabit speeds by treating them as bit-stream payload defined in Section 3.3.3 of [RFC3985].¶
The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD", "SHOULD NOT", "RECOMMENDED", "NOT RECOMMENDED", "MAY", and "OPTIONAL" in this document are to be interpreted as described in BCP 14 [RFC2119] [RFC8174] when, and only when, they appear in all capitals, as shown here.¶
Similar to [RFC4553] and [RFC5086] the term Interworking Function (IWF) is used to describe the functional block that encapsulates bit streams into PLE packets and in the reverse direction decapsulates PLE packets and reconstructs bit streams.¶
The generic models defined in [RFC4664] are applicable to PLE.¶
PLE embraces the minimum intervention principle outlined in section 3.3.5 of [RFC3985] whereas the data is flowing through the PLE encapsulation layer as received without modifications.¶
For some applications the NSP function is responsible for performing operations on the native data received from the CE. Examples are terminating FEC in case of 100GE or terminating the OTUk layer for OTN. After the NSP the IWF is generating the payload of the VPWS which carried via a PSN tunnel.¶
|<--- p2p L2VPN service -->|
| |
| |<-PSN tunnel->| |
v v v v
+---------+ +---------+
| PE1 |==============| PE2 |
+---+-----+ +-----+---+
+-----+ | N | | | | N | +-----+
| CE1 |-----| S | IWF |.....VPWS.....| IWF | S |-----| CE2 |
+-----+ ^ | P | | | | P | ^ +-----+
| +---+-----+ +-----+---+ |
CE1 physical ^ ^ CE2 physical
interface | | interface
|<--- emulated service --->|
| |
attachment attachment
circuit circuit
To allow the clock of the transported signal to be carried across the PLE domain in a transparent way the network synchronization reference model and deployment scenario outlined in section 4.3.2 of [RFC4197] is applicable.¶
J
| G
v |
+-----+ +-----+ v
+-----+ |- - -|=================|- - -| +-----+
| |<---------|.............................|<---------| |
| CE1 | | PE1 | VPWS | PE2 | | CE2 |
| |--------->|.............................|--------->| |
+-----+ |- - -|=================|- - -| +-----+
^ +-----+<-------+------->+-----+
| | ^
A +-+ |
|I| E
+-+
The attachment circuit clock E is generated by PE2 via a differential clock recovery method in reference to a common clock I. For this to work the difference between clock I and clock A MUST be explicitly transferred between the PE1 and PE2 using the timestamp inside the RTP header.¶
For the reverse direction PE1 does generate the clock J in reference to clock I and the clock difference between I and G.¶
The way the common clock I is implemented is out of scope of this document. Well established concepts for achieving frequency synchronization in a PSN have already been defined in [G.8261] and can be applied here as well.¶
The basic packet format used by PLE is shown in the Figure 3.¶
+-------------------------------+ -+
| PSN and VPWS Demux | \
| (MPLS/SRv6) | > PSN and VPWS
| | / Demux Headers
+-------------------------------+ -+
| PLE Control Word | \
+-------------------------------+ > PLE Header
| RTP Header | /
+-------------------------------+ --+
| Bit Stream | \
| Payload | > Payload
| | /
+-------------------------------+ --+
This document does not imply any specific technology to be used for implementing the VPWS demultiplexing and PSN layers.¶
When a MPLS PSN layer is used. A VPWS label provides the demultiplexing mechanism as described in section 5.4.2 of [RFC3985]. The PSN tunnel can be a simple best path Label Switched Path (LSP) established using LDP [RFC5036] or Segment Routing [RFC8402] or a traffic engineered LSP established using RSVP-TE [RFC3209] or SR-TE [SRPOLICY].¶
When PLE is applied to a SRv6 based PSN, the mechanisms defined in [RFC8402] and the End.DX2 endpoint behavior defined in [SRV6NETPROG] do apply.¶
The PLE header MUST contain the PLE control word (4 bytes) and MUST include a fixed size RTP header [RFC3550]. The RTP header MUST immediately follow the PLE control word.¶
The format of the PLE control word is in line with the guidance in [RFC4385] and as shown in Figure 4:¶
0 1 2 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|0 0 0 0|L|R|RSV|FRG| LEN | Sequence number |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
The first nibble is used to differentiate if it is a control word or Associated Channel Header (ACH). The first nibble MUST be set to 0000b to indicate that this header is a control word as defined in section 3 of [RFC4385].¶
The other fields in the control word are used as defined below:¶
L¶
R¶
RSV¶
FRG¶
LEN¶
Sequence Number¶
The RTP header MUST be included and is used for explicit transfer of timing information. The RTP header is purely a formal reuse and RTP mechanisms, such as header extensions, contributing source (CSRC) list, padding, RTP Control Protocol (RTCP), RTP header compression, Secure Realtime Transport Protocol (SRTP), etc., are not applicable to PLE VPWS.¶
The format of the RTP header is as shown in Figure 5:¶
0 1 2 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|V=2|P|X| CC |M| PT | Sequence Number |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
| Timestamp |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
| Synchronization Source (SSRC) Identifier |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
V: Version¶
P: Padding¶
X: Header Extension¶
CC: CSRC Count¶
M: Marker¶
PT: Payload Type¶
Sequence Number¶
Timestamp¶
SSRC: Synchronization Source¶
A bit-stream is mapped into a PLE packet with a fixed payload size which MUST be defined during VPWS setup, MUST be the same in both directions of the VPWS and MUST remain unchanged for the lifetime of the VPWS.¶
All PLE implementations MUST be capable of supporting the default payload size of 1024 bytes.¶
The PLE payload is filled with incoming bits of the bit-stream starting from the most significant to the least significant bit without considering any structure of the bit-stream.¶
For PCS based attachment circuits supporting FEC the NSP function MUST terminate the FEC and pass the PCS encoded signal to the IWF function.¶
For PCS based attachment circuits supporting virtual lanes (i.e. 100GE) a PLE payload MUST carry information from all virtual lanes in a bit interleaved manner after the NSP function has performed PCS layer de-skew and re-ordering.¶
A PLE implementation MUST support the structure agnostic payload for all bit-streams except the following:¶
In case of OTN bit-streams, the NSP function MUST present to the IWF an extended ODUk including a valid frame alignment overhead. The IWF is performing byte-aligned mapping into PLE packets. The egress NSP function will recover the ODUk by searching for the frame alignment overhead.¶
For byte aligned payloads PLE uses the following order for packetization:¶
All PLE implementations MUST support the transport of OTN bit-streams using the byte aligned payload.¶
In IEEE 802.3BS the PCS layer for 200GBASE-R and 400GBASE-R is defined with the functions shown in Figure 6.¶
Reconciliation Sublayer (RS)
| ^
v |
+-----------------+ +-----------------+
| encode and rate | | decode and rate |
| matching | | matching |
+-----------------+ +-----------------+
v ^
+-----------------+ +-----------------+
| 256B/257B | | reverse |
| transcode | | transcode |
+-----------------+ +-----------------+
v ^
+-----------------+ +-----------------+
| scramble | | descramble |
+-----------------+ +-----------------+
v ^
+-----------------+ +-----------------+
| alignment | | alignment |
| insertion | | removal |
+-----------------+ +-----------------+
| ^ <-- IWF boundary
+-----------------------------------------------+
| v | |
| +-----------------+ +-----------------+ |
| | pre-FEC | | post-FEC | |
| | distribution | | interleave | |
| +-----------------+ +-----------------+ |
| v ^ |
| +-----------------+ +-----------------+ |
| | FEC encode | | FEC decode | |
| +-----------------+ +-----------------+ |
| v ^ |
| +-----------------+ +-----------------+ |
| | distribution | | lane reorder | |
| | & interleave | | & de-interleave | |
| +-----------------+ +-----------------+ |
| | ^ |
| | +-----------------+ |
| | | alignment lock | |
| | NSP | lane deskew | |
| | +-----------------+ |
| | ^ |
| v | |
| Physical Medium Attachment (PMA) |
+-----------------------------------------------+
For 200GBASE-R and 400GBASE-R bit-streams, on ingress the NSP function will perform alignment lock and lane de-skew, lane order and de-interleave, FEC decode and post-FEC interleave as shown in Figure 6. After the post-FEC interleave the NSP function will create a stream of 10280 bit blocks (comprising of two 5140 code blocks).¶
On the egress the IWF sends a stream of 10280 bit blocks to the NSP function and which performs pre-FEC distribution, FEC encode and distribute and interleave functions as shown in Figure 6.¶
In the 10280 bit block stream, alignment markers exist every 4096, 10280 bit blocks (8192 code blocks) for 400GBASE-R and every 2048, 10280 bit blocks (4096 code blocks) for 200GBASE-R.¶
On ingress the NSP must indicate to the IWF when a code word carries an alignment marker (or every n-th alignment marker where n is a multiple of 2). The IWF will create a PLE packet with the alignment marker bits at the beginning of the PLE payload. Considering the default PLE payload size of 1024 bytes, the PLE payload will contain the first 8096 bits (1024 bytes) of the 10280 bit block in the first packet. The following PLE packets will contain the remaining bits followed by the next 10280 bits.¶
The egress NSP will recover the 10280 bit block by searching for the alignment markers at the beginning of PLE packets and recover the 10280 bit block stream.¶
For the 10280 bit data streams the NSP will use the following order of packetization.¶
With the default payload size of 1024 bytes the alignment markers will be present at the start of every 5140-th PLE packet for 400GBASE-R and every 2570-th PLE packet for 200GBASE-R.¶
Non-default payload sizes must be chosen so that alignment markers will always be at the start of every N-th packet.¶
Alignment of the signal may use the alignment marker state machine defined in IEEE802.3BS.¶
A PLE VPWS can be established using manual configuration or leveraging mechanisms of a signaling protocol¶
Furthermore emulation of bit-stream signals using PLE is only possible when the two attachment circuits of the VPWS are of the same type (OC192, 10GBASE-R, ODU2, etc) and are using the same PLE payload type and payload size. This can be ensured via manual configuration or via a signaling protocol¶
Extensions to the PWE3 [RFC4447] and EVPN-VPWS [RFC8214] control protocols are described in a separate document [PLESIG].¶
After the VPWS is set up, the PSN-bound IWF does perform the following steps:¶
The CE-bound IWF is responsible for removing the PSN and VPWS demultiplexing headers, PLE control word and RTP header from the received packet stream and play-out of the bit-stream to the local attachment circuit.¶
A de-jitter buffer MUST be implemented where the PLE packets are stored upon arrival. The size of this buffer SHOULD be locally configurable to allow accommodation of specific PSN packet delay variation expected.¶
The CE-bound IWF SHOULD use the sequence number in the control word to detect lost and mis-ordered packets. It MAY use the sequence number in the RTP header for the same purposes.¶
The payload of a lost packet MUST be replaced with equivalent amount of replacement data. The contents of the replacement data MAY be locally configurable. All PLE implementations MUST support generation of "0xAA" as replacement data. The alternating sequence of 0s and 1s of the "0xAA" pattern does ensure clock synchronization is maintained. While playing out the replacement data, the IWF will apply a holdover mechanism to maintain the clock.¶
Whenever the VPWS is not operationally up, the CE-bound NSP function MUST inject the appropriate native downstream fault indication signal (for example ODUk-AIS or ethernet LF).¶
Whenever a VPWS comes up, the CE-bound IWF enters the intermediate state, will start receiving PLE packets and will store them in the jitter buffer. The CE-bound NSP function will continue to inject the appropriate native downstream fault indication signal until a pre-configured amount of payloads is stored in the jitter buffer.¶
After the pre-configured amount of payload is present in the jitter buffer the CE-bound IWF transitions to the normal operation state and the content of the jitter buffer is played out to the CE in accordance with the required clock. In this state the CE-bound IWF MUST perform egress clock recovery.¶
The recovered clock MUST comply with the jitter and wander requirements applicable to the type of attachment circuit, specified in:¶
Whenever the L bit is set in the PLE control word of a received PLE packet the CE-bound NSP function SHOULD inject the appropriate native downstream fault indication signal instead of playing out the payload.¶
If the CE-bound IWF detects loss of consecutive packets for a pre-configured amount of time (default is 1 millisecond), it enters packet loss (PLOS) state and a corresponding defect is declared.¶
If the CE-bound IWF detects a packet loss ratio (PLR) above a configurable signal-degrade (SD) threshold for a configurable amount of consecutive 1-second intervals, it enters the degradation (DEG) state and a corresponding defect is declared. Possible values for the SD-PLR threshold are between 1..100% with the default being 15%. Possible values for consecutive intervals are 2..10 with the default 7.¶
While either a PLOS or DEG defect is declared the CE-bound NSP function SHOULD inject the appropriate native downstream fault indication signal. Also the PSN-bound IWF SHOULD set the R bit in the PLE control word of every packet transmitted.¶
The CE-bound IWF does change from the PLOS to normal state after the pre-configured amount of payload has been received similarly to the transition from intermediate to normal state.¶
Whenever the R bit is set in the PLE control word of a received PLE packet the PLE performance monitoring statistics SHOULD get updated.¶
PLE SHOULD provide the following functions to monitor the network performance to be inline with expectations of transport network operators.¶
The near-end performance monitors defined for PLE are as follows:¶
Each second with at least one packet lost or a PLOS/DEG defect SHALL be counted as ES-PLE. Each second with a PLR greater than 15% or a PLOS/DEG defect SHALL be counted as SES-PLE.¶
UAS-PLE SHALL be counted after configurable number of consecutive SES-PLE have been observed, and no longer counted after a configurable number of consecutive seconds without SES-PLE have been observed. Default value for each is 10 seconds.¶
Once unavailability is detected, ES and SES counts SHALL be inhibited up to the point where the unavailability was started. Once unavailability is removed, ES and SES that occurred along the clearing period SHALL be added to the ES and SES counts.¶
A PLE far-end performance monitor is providing insight into the CE-bound IWF at the far end of the PSN. The statistics are based on the PLE-RDI indication carried in the PLE control word via the R bit.¶
The PLE VPWS performance monitors are derived from the definitions in accordance with [G.826]¶
The PSN carrying PLE VPWS may be subject to congestion, but PLE VPWS representing constant bit-rate (CBR) flows cannot respond to congestion in a TCP-friendly manner as described in [RFC2913].¶
Hence the PSN providing connectivity for the PLE VPWS between PE devices MUST be Diffserv [RFC2475] enabled and MUST provide a per domain behavior [RFC3086] that guarantees low jitter and low loss.¶
To achieve the desired per domain behavior PLE VPWS SHOULD be carried over traffic-engineering paths through the PSN with bandwidth reservation and admission control applied.¶
As PLE is leveraging VPWS as transport mechanism the security considerations described in [RFC7432] and [RFC3985] are applicable.¶
Applicable signaling extensions are out of the scope of this document.¶
PLE does not introduce additional requirements from IANA.¶
The authors would like to thank Andreas Burk for reviewing this document and providing useful comments and suggestions.¶